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| 001 | ocn779165215 | ||
| 003 | OCoLC | ||
| 005 | 20171224113850.0 | ||
| 006 | m o d | ||
| 007 | cr cnu---unuuu | ||
| 008 | 120305s2012 njua o 001 0 eng d | ||
| 010 | _z 2011043303 | ||
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| 020 | _z9781118243046 | ||
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_a10.1002/9781118273142 _bWiley InterScience _nhttp://www3.interscience.wiley.com |
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_a621.3815 _223 |
| 049 | _aMAIN | ||
| 100 | 1 | _aDoman, David. | |
| 245 | 1 | 0 |
_aEngineering the CMOS library : _benhancing digital design kits for competitive silicon / _cDavid Doman. |
| 260 |
_aHoboken, N.J. : _bJohn Wiley & Sons, _c©2012. |
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_a1 online resource (iv, 327 pages) : _billustrations |
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_atext _btxt _2rdacontent |
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_acomputer _bc _2rdamedia |
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_aonline resource _bcr _2rdacarrier |
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_a"This book is about gaining a competitive edge in the Integrated Circuit IC marketplace. It suggests that there is an unrecognized value hidden in the safety margins of descriptive views in any piece of intellectual property (IP). This hidden value is normally left on the table. However, it can be used by the aggressive design engineer (or manager) to surpass the competition in the marketplace. This text reveals how the typical design house can enhance performance, reduce power, and improve the density of standard-cell logic. It will show how to add value to the generic, foundry-provided standard-cell library that most companies use without modification. Lastly, it identifies the low-risk opportunities aggressive designers and managers can employ to improve margin from overdesigned standard cells."-- _cProvided by publisher. |
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| 520 |
_a"This book is about gaining a competitive edge in the Integrated Circuit IC marketplace"-- _cProvided by publisher. |
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| 505 | 0 | _aFrontmatter -- Introduction -- Stdcell Libraries -- IO Libraries -- Memory Compilers -- Other Functions -- Physical Views -- Spice -- Timing Views -- Power Views -- Noise Views -- Logical Views -- Test Views -- Consistency -- Design for Manufacturability -- Validation -- Playing with the Physical Design Kit: Usually ₃At Your Own Risk₄ -- Tagging and Revisioning -- Releasing and Supporting -- Other Topics -- Communications -- Appendix I: Minimum Library Synthesis Versus Full-Library Synthesis of A Four-Bit Flash Adder -- Appendix II: Pertinent CMOS Bsim Spice Parameters with Units and Default Levels -- Appendix III: Definition of Terms -- Appendix IV: One Possible Means of Formalized Monthly Reporting -- Index. | |
| 588 | 0 | _aPrint version record. | |
| 650 | 0 |
_aDigital integrated circuits _xDesign and construction. |
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| 650 | 0 | _aMetal oxide semiconductors, Complementary. | |
| 650 | 0 | _aIndustrial efficiency. | |
| 650 | 4 |
_aDigital integrated circuits _xDesign and construction. |
|
| 650 | 4 | _aMetal oxide semiconductors, Complementary. | |
| 650 | 4 | _aIndustrial efficiency. | |
| 650 | 7 |
_aTECHNOLOGY & ENGINEERING _xElectronics _xCircuits _xVLSI & ULSI. _2bisacsh |
|
| 650 | 7 |
_aTECHNOLOGY & ENGINEERING _xElectronics _xCircuits _xGeneral. _2bisacsh |
|
| 650 | 7 |
_aTECHNOLOGY & ENGINEERING _xElectronics _xCircuits _xIntegrated. _2bisacsh |
|
| 650 | 7 |
_aDigital integrated circuits _xDesign and construction. _2fast _0(OCoLC)fst00893696 |
|
| 650 | 7 |
_aIndustrial efficiency. _2fast _0(OCoLC)fst00970970 |
|
| 650 | 7 |
_aMetal oxide semiconductors, Complementary. _2fast _0(OCoLC)fst01017635 |
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| 650 | 7 |
_aDigital integrated circuits / Design and construction. _2local |
|
| 650 | 7 |
_aMetal oxide semiconductors, Complementary. _2local |
|
| 650 | 7 |
_aIndustrial efficiency. _2local |
|
| 655 | 4 | _aElectronic books. | |
| 710 | 2 | _aWiley InterScience (Online service) | |
| 776 | 0 | 8 |
_iPrint version: _aDoman, David. _tEngineering the CMOS library. _dHoboken, N.J. : John Wiley & Sons, ©2012 _z9781118243046 _w(DLC) 2011043303 _w(OCoLC)755700209 |
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